1. Field of the Invention
The invention relates in general to a method of manufacturing a flash memory device and, more particularly, to a method of manufacturing a flash memory device, wherein damage to the sidewalls of a semiconductor substrate of a region exposed when a control gate and a floating gate are formed can be prevented.
2. Discussion of Related Art
A NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim tunneling (FN). The NAND flash memory device provides a large capacity and a high level of integration.
The NAND flash memory device includes a number of cell blocks. Each cell block includes a number of cell strings in which a number of cells for storing data are connected in series to form one string, and a drain select transistor and a source select transistor formed between the cell string and the drain, and the cell string and the source, respectively.
The cell of the NAND flash memory device is formed by forming an isolation layers on a predetermined region of a semiconductor substrate, forming a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are laminated on a predetermined region of the semiconductor substrate, and forming a junction at both sides of the gate.
In a NAND flash memory device of 60 nm or less, however, a method of forming high a conductive layer for a floating gate and performing a trench etch process for forming an isolation layers simultaneously with an etch process of the conductive layer is used in order to secure the overlap margin of the floating gate and the active region at the same time and to prevent a thinning phenomenon of the tunnel oxide layer.
In the case where the method is used, a process of controlling the EFH (effective field oxide height) by etching the isolation layers to a predetermined depth using a wet etch process must be implemented subsequently in order to increase the junction area of the dielectric layer and the floating gate. However, as the conductive layer for the floating gate of a region exposed at the time of the formation of the control gate and the floating gate subsequently is etched, the isolation layers is further etched.
Accordingly, the isolation layers is formed lower in depth than a surface of the semiconductor substrate. If the isolation layers is formed lower in depth than the surface of the semiconductor substrate as described above, the sidewalls of the semiconductor substrate are exposed. As a result, the exposed portions of the semiconductor substrate are damaged in a subsequent process, leading to fatal damage to the device.